Simulation and Analysis of Fully Adiabatic Circuit Designing with Single Power Clock for High-Frequency Low-Power VLSI Circuits

  •  Yashu Swami    


Adiabatic logic guarantees vast diminishments of power utilization since it doesn't disperse power. This paper audits ongoing advancements in adiabatic circuits. First, the fully adiabatic circuit designing technology called pass-transistor adiabatic logic (PTAL) is discussed. Next, the operation of the dual-rail logic and the power clock supply with the logic operation of the PTAL technology is discussed. Further, many basic logic circuits using the PTAL technology are designed, compiled, and simulated. Finally, the performance results, power dissipation, speed, efficiency, and load analysis of the circuits are compared with the conventional and existing CMOS technologies under the same simulation conditions using standard 45nm technology with VDD = 1V and prove that even at high frequencies above 2GHz, it can outperform the dominating conventional CMOS logic designing in the field of power dissipation. The simulation results are provided to support our claim. We used 45nm technology for all our simulations.

This work is licensed under a Creative Commons Attribution 4.0 License.
  • ISSN(Print): 1913-8989
  • ISSN(Online): 1913-8997
  • Started: 2008
  • Frequency: quarterly

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