Abstract

A systematic approach to CMOS Low Noise Amplifier design is presented. This approach uses an input impedance matching technique based on LC Ladder filters which will provide suitable input matching in any arbitrary band (S11<-10dB), also S22 is about -10 dB in average. Using cascode structure, maximum power gain about 25 dB is achievable. Noise level is less than 3 dB over the full band of UWB. Power dissipation of this amplifier is only 8.5 mw and operates with 0.85 v supply voltage while 0.13 µm CMOS technology is used.

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