Efficiency Analysis of Low Power ClassE Power Amplifier

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 μm CMOS technology.


Introduction
High efficiency and low level output power design of power amplifier (PA) is a requirement for optimization of the energy efficiency of the transmitter which is one the key building blocks of sensor nodes in wireless sensor networks.The class-E power amplifier can ideally achieve 100% efficiency.This high efficiency has spurred many research interests on the design and analysis of Class-E Pas (Apostolidou, et al, 2009;Lee, et al 2010;Brama, et al, 2008;Mertens, et al, 2002;Tsai, et al, 1999;Reynaert, 2006).The conventional class-E power amplifier can produce large power levels with good efficiency (Lee, et al 2010;Brama, et al, 2008;Mertens, et al, 2002.Most of the existing Class-E PA designs have been optimized to work at high output power levels, ranging from 23 to 33 dBm (Lee, et al 2010;Brama, et al, 2008;Mertens, et al, 2002;Tsai, et al, 1999;Reynaert, 2006;Mousa, 2013).If these fully integrated PAs are used in applications requiring low level output power such as wireless body sensor networks, the overall efficiency significantly degrades (Tan, et al, 2012).For example Bluetooth and ZigBee standards are short range standards that their output power level are from 0 to 10 dBm (Retz, et al, 2009;Eo,et al, 2007;Bae, et al, 2011) and in wireless body sensor networks it is even under 0 dBm (Cook, et al, 2006;Tan, et al, 2012).Therefore, high efficiency PA with low level output power is critical to short range wireless sensor network.
The efficiency of low power class-E power amplifier (LPCEPA) introduced by Jun Tan (Tan,et al, 2012) is appropriate for use in transmitter block of the sensor node in short range wireless sensor networks.LPCEPA architecture is a proper option for fully integrated PA solutions.Among the elements of a fully integrated design, on chip inductors have large losses than the others and have the most adverse effect on overall efficiency of the transmitter.
In this paper, to investigate the effect of inductor losses on LPCEPA efficiency, the equations of losses of elements and efficiency of PA vs. losses are derived and based on these observations an appropriate PA has been proposed.
The rest of this paper is organized as follows: In Section 2, the circuitry of the LPCEPA and circuit description is presented.Section 3 presents the analytical equations of the losses.In section 4, simulation results of the proposed PA are presented.Section 5 concludes the paper.

Circuit Description
With the following assumptions, the circuit model of LPCEPA shown in Figure 1 has been selected for evaluation.In the analysis of PA, except the resistor R L , all of the elements are supposed to be ideal and the transistor is an ideal switch with zero and infinite resistance when turns on and off, respectively.Two equations define the class-E PA conditions, as below: (Apostolidou, et al, 2009;Lee, et al 2010;Brama, et al, 2008;Mertens, et al, 2002;Tsai, et al, 1999;Reynaert, 2006) where t 1 is the time that switch turns on.
This equivalent circuit consists of a switch shunt capacitance C 0 , matching network and load resistor R L .For the analysis, suppose that frequency of input signal, voltage of power supply and duty cycle are known variables.Unknown variables in the circuitry of Figure 1 are six variables; C 0 , C 1 , C 2 , C 3 , L 0 and L 1 .To find unknown variables, six independent equations are required.Four new design variables are defined as: where C eq denotes the total capacitance at node V 1 ,  is the ratio of C 1 to C 1 +C 2 ,  is the ratio of parallel capacitance C 0 to C eq and q is the normalized frequency.The design challenge is to compute these four new variables.Once calculated, the value of the real elements C 0 ~C2 and L 0 can be specified.The two variables I a and  are concluded next.When the switch is off, KCL equations at nodes V 1 and V 2 are: and the voltage drops across the inductor L 0 are as follows for the time switch is off and when it is on, respectively.
When the switch is ON, node V 2 requires: Solving differential equations, the waveform of V 1 , V 2 and I L when switch is off are: The variable  is defined as: For determining A 1 , A 2 and , boundary conditions of voltage waveform V 1 can be used.The initial condition of Solving the linear algebraic equations, the variables of A 1 , A 2 and  are: (sin( ) sin( ) sin( ) sin( )) sin( ) sin( ) .sin( ) sin( ) 2 sin( ) sin( ) sin( ) sin( ) 2 sin( ) sin( ) sin( ) and for the time interval that switch is on, V 1 is zero.Also, the current of inductor L 0 is: By solving differential equation ( 10), V 2 can be calculated as: to satisfy that all waveforms are periodic with the period of T,  is: The variables a 1 , a 2 , a 3 , a 4 , a 5 , k 1 , k 2 , k 3 , g 1 , g 2 and g 3 used in equation above are given in the Appendix A. The output impedance Z out at the first frequency can be computed by: Because V 2 is a periodic waveform, it can be expanded into its Fourier series.At the first frequency ω 0 , Z out is: V 2 _ 1 and  1 are amplitude and phase of the fundamental harmonic of V 2 , respectively.From ( 21) and ( 22) equations, the C 3 and L 1 can be calculated.
With computing average current of L 0 inductor, consumption power can be calculated as below: The variable h is given in the Appendix A

Analysis of Power Losses and Efficiency
In analysis of losses of LPCEPA, losses of elements are shown by a resistor in series with elements.Figure 2 shows the equivalent circuit of the power amplifier.The r L0 and r L1 are losses of the inductors L 0 and L 1 , respectively.To simplify derivation of loss equations for inductors, root means square (RMS) current of L 0 inductor and maximum current of L 1 inductor are determined with suppose that currents of elements stay no changed when parasitic resistance are not zero.
The RMS current of inductor L 0 is: and power loss in L0 inductor is determined by: For the time in which the switch is OFF (0<t<t1) iL0 is presented by equation 13 and for ON time of the switch it is given by equation 18.By integrating current from 0 to t 1 and from t 1 to T, Irms,L 0 can be calculated as: where variables E 1 ~ E 7 are given in the Appendix B.
The current that flows through capacitor C0 is: The RMS current of capacitor C 0 is given by equation 30.
The power loss in shunt capacitor C 0 is shown in equation 31.Same procedure for capacitors C 1 and C 2 is done and equation for their current, RMS current and power loss are given by equations 32 ~ 37.
And its power loss is: To calculate losses of switch resistance, its current must be known.When switch is open, its current is zero and when it's closed, its current is calculated using KCL in V 1 node as follows: (40) and its RMS value is calculated by: then, the losses of switch is:

Simulation Results
The purpose of design of the LPCEPA is to be used in the transmitter of a short range wireless sensor network structure.Major advantages of LPCEPA are low level output power, high efficiency and on chip implementation of all elements.Since on chip inductors have large losses than the other elements, their effect on overall efficiency of PA has been discussed.To investigate the losses of on chip inductors in the PA, a schematic of LPCEPA (Figure 2) has been simulated with element values listed in Table1 using Cadence Spectre.Furthermore, equations governing this structure have been evaluated in MATLAB.In these simulations, only the losses of inductors and switch have been considered.Waveforms of the voltage of the drain terminal and the current of the inductor L 0 are shown in the Figure 3. Figure 4 shows the efficiency versus the losses of L 0 , L 1 and switch when considered separately and together.Figure 5 shows the same for MATLAB evaluation.Considering the efficiency analysis of the amplifier it can be concluded that to decrease the losses, output network can be changed such that the first harmonic RMS current does not pass through the inductor.To do this, we propose the following circuit.Simulation results for two structures show about 13 % improvement in efficiency.
Figure 6.Proposed PA To investigate the results, structures of Figure 1 and Figure 6 have been simulated using the component values listed in Table 2. PAE of both circuits versus series loss of inductors have been shown in Figure 8.For a 4-ohm series resistance, the difference in PAE of two circuits is 19%.Also, the analysis of both structures employing on chip inductors for -2 dBm output power at 400 MHz frequency shows that PAE of circuit LPCEPA (Figure 1) is 20% and that of circuit proposed PA (Figure 6) is 33%.Results are summarized in Table 3.
The proposed fully integrated amplifier for 400 MHz and -2 dBm has been shown in Figure 6.Component values are listed in Table 2.As supply voltage varies from 0.35 V to 0.6 V the output power varies from -3.1 dBm to 1.1 dBm (Figure 9).----------4 Table 3. Results of the amplifiers of Fig. 1 and Fig. 6 for the component values listed in Table 1

Conclusion
In this paper, the effect of element losses on PA efficiency has been investigated.Since LPCEPA is suitable for fully integrated implementation and among the integrated elements on chip inductors have larger losses, equations for the efficiency have been derived and plotted versus the value of inductors losses.Results show that one of the inductors has larger contribution to the overall drop in efficiency.Derived equations are evaluated using MATLAB.Cadence Spectre has been used for schematic simulation.A fair matching between simulated power loss and efficiency and MATLAB evaluations can be seen from the plots.Considering the analysis, the proposed power amplifier shows about 13 % improvement in power efficiency at 400 MHz and -2 dBm output power level.The proposed PA is simulated in 0.18 μm CMOS technology. 2 sin( )sin( ) 2cos( ) cos( ) 2 (cos( ) 1)(1 cos( )) 2 cos( ) ( 1) ( 1) ( 1) ( 1)

Figure 3 .
Figure 3. Waveforms of the drain node voltage and L 0 inductor current

Figure 4 .
Figure 4. Efficiency of PA versus losses of inductors and switch (Cadence Spectre)

Figure 7 .Circuitry
Figure 7. Efficiency of LPOCEPA versus losses of inductors (Cadence Spectre) with 2.4 GHz Total power loss in the LPCEPA is the sum of power loss in inductors L 0 and L 1 and power loss in capacitances C 0 ~C3 .

Table 1 .
Simulation parameters and element values for simulated