Interface between the Embedded Processor Nios and the TDC Module and its Application

This paper introduces a design method for SOPC (System on Programmable Chip) based on embedded Nios II soft-core processor. The interface between the soft-core processor Nios II and the TDC module is given, and the initial programming technique and Nios II application programme is explained at the same time.


Introduction
High-resolution time interval measurement has been widely applied in the aerospace, communications, digital television broadband radar, logic analyzer, Digital Storage Oscilloscope modern testing equipment etc.With public transportation, technology, defense of the rapid development and awareness of precision measuring instruments growing, the demanding of ultra short optical pulses between narrow time interval and pulses high-precision measurement have become a remarkable research projects .TDC exclusive use of time-to-digital converter chip with Nios II soft-core processor time interval is a measurement system to achieve high precision measurement of the effective methods.The advantage is: High accuracy, debugging simple, low power consumption, real-time data processing, human-machine interface humanity, remote operation and owning embedded operating system.This work focuses on the following embedded Nios II soft-core processor and TDC-GP1 time-to-digital converter chip interface circuit and programming technology.

NIOSII Soft-Core Processor
A Nios II processor system is equivalent to a microcontroller or "computer on a chip" that includes a processor and a combination of peripherals and memory on a single chip.The term "Nios II processor system" refers to a Nios II processor core, a set of on-chip peripherals, onchip memory, and interfaces to off-chip memory, all implemented on a single Altera device.(Altera, 2005)Like a microcontroller family, all Nios II processor systems use a consistent instruction set and programming model.

1.1Nios II Processor System Basics
The Nios II processor is a general-purpose RISC processor core providing: Altera's SOPC Builder design tool fully automates the process of configuring processor features and generating a hardware design that you program into an FPGA.The SOPC Builder graphical user interface (GUI) enables you to configure Nios II processor systems with any number of peripherals and memory interfaces.You can create entire processor systems without performing any schematic or hardware description-language (HDL) design entry.SOPC Builder can also import HDL design files, providing an easy mechanism to integrate custom logic into a Nios II processor system.After system generation, you can download the design onto a board, and debug software executing on the board.To the software developer, the processor architecture of the design is set.Software development proceeds in the same manner as for traditional, on-configurable processors.The 8 events of the two channels can arbitrarily be measured against one another.Negative times can also be measured.

TDC-GP1 chip brief Introduction
The resolution can be adjusted accurately via software in the 'resolution adjust' mode.
Ports to measure capacities, coils or resistors

Variable edge sensitivity of the measuring inputs
Internal ALU for the calibration of the measurement result.A 24-Bit multiplication unit enables the results to be scaled.
Wide range for the reference clock: 500 KHz -35 MHz Surface mount TQFP44 package.
Extremely low power consumption, fully battery operation possible 8-bit processor-interface TDC-GPl provides with the external processor interface, including eight data buses, 4 bit can operate 16 Registers address line, read, write, film elections, and so on.Another, to simplify the interface design, also provided the address latches line (ALE).The internal chip has 7 only write registers, 4 can write value control registers, 8 only read results registers.External processor control to write control registers and value registers through the address line, writing, film elections, latches, etc.By controlling different addresses on the value of the control register, the chip can initialize, choose different working conditions and adjust the edge signal sensitivity.After measuring, the chip interruption activate the external processor to start reading the results register, the results are worth reading to further optimize the processor computation, storage and output display.Application of the range1 Register is set to: Reg0:0x44; Regl: 0x4D; Reg2:0x01; Reg3:0xXX: Reg4: OxXX; Reg5:0xXX; Reg6:Ox02; Reg7:0x01; Reg8:0x00; Reg9:0x00; Regl0:0x80.

NiosII and TDC-GPl interface circuit
Embedded Processor NiosII put TDC -GPl module interface equipment as PIO for the general operation.Therefore TDC data module |, address, the election unit, literacy signals are included in the PIO Bus.Its interface circuit shown in figure 1,which TDC_DB [7 .. 0] of the eight data lines, control will be responsible for order entry to the control registers and results data from the results registers were read out; TDC_AD [3 .. 0] to address data line; TDC_ALE to address latches; TDC_CEN signal for the election unit; TDC_WRN to enable writing; TDC_RDN to enable reading; INTFLAG signs of disruption; START signal to begin; STOP 1 received no signal delay; STOP 2 received signal delay.
Figure 1.Interface between the Embedded Processor Nio and theTDC Module

NiosII and TDC interface chip
Nios II processor uses modular structure software, including;(1)TDC-GPl initialization,(2) setting TDC-GPl chip channel,(3) working mode setting, (4)measurement the results,(5)measurement data display,(6)measurement data storage.For example, TDC -GPl can work in precision adjustable model.After the measurement, the results will be shown as the following a series of manipulations:(1) TDC chip be set in the state of writing through the assignment Control Register 7 shielding all of the input signal STOP.
(3) Pointer at the control register 0, the chip work in a range 1, self-calibration mode characterized by a number of functions.Then write control register 1, the chips achieve precision adjustable, adjustable work on the accuracy of mode l.(4) Write control register 2.The result is that, The first pulse of channel two rise time and the access an article a pulse rise time for the poor.(5) Write control register 7, the abolition of the two channels on the STOP input signal shielding.Read measurements, circuit is SCM inquiries TDC -GPl chip interrupted output pins, chip interrupted when issued, that is, enter the break in service procedures in the home TDC chip in the reading of the state, NiosII processor visits the results register and read the results.(Liu, 2004).Then niosII processor computate and show the results, the following is the main part of the NiosII interface procedures.

Initialization TDC-GPl
As Embedded Processor NioslI put TDC-GPl module interface as ordinary operate equipment PIO; blocks all the data through IOWR_ALTERA_AVALON_PIO_DIRECTIO N (PIO base address, data) order to register for the PIO write, IORD_ALTERA_AVALON_PIO_DATA (PIO base address) orders reading operation.Below is the initialization procedures: Void

Full 32 -
bit instruction set, data path, and address space 32 general-purpose registers 32 external interrupt sources Single-instruction 32 ?32 multiply and divide producing a 32-bit result Dedicated instructions for computing 64-bit and 128-bit products of multiplication Floating-point instructions for single-precision floating-point operations Single-instruction barrel shifter Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals Hardware-assisted debug module enabling processor start, stop, step and trace under integrated development environment (IDE)control Software development environment based on the GNU C/C++ tool chain and Eclipse IDE Integration with Altera®'s Signal Tap® II logic analyzer, enabling realtime analysis of instructions and data along with other signals in the FPGA design Instruction set architecture (ISA) compatible across all Nios II processor systems Performance up to 250 DMIPS TDC -GP1 chip is a dual-channel Universal time-to-digital converter chip, with the largest range of 200ms and accuracy of 125 ps.Chip supports two working range and kinds of work patterns and it has flexible work practices.TDC-GP1 use 44 pin TQFP package with TDC measurement unit, 16-ALU, RLC measurement unit and eight processor interface modules.The pin names and functions are listed in finished 3.2 Measurement showed unit Void measure_TDC () {Int valid = 0;