A Nonuniform Reference Voltage Optimization Based on Relative-Precision-Loss Ratios in MLC NAND Flash Memory

In Multi-Level-Cell (MLC) NAND flash memory, cell-to-cell interference (CCI) and retention time have become the main noise that degrades the data storage reliability. To mitigate such noise, a relative precision loss (RPL) nonuniform reference voltage sensing strategy is proposed in this paper. First, based on the NAND flash channel model with CCI and retention noise, we simulate the data storage process of MLC NAND flash by Monte Carlo method, and find that the threshold-voltage of each disturbed storage state shows approximately to be Gaussian distributed. Then, by Gaussian approximation, the distribution of threshold voltage can be estimated easily in mathematics with a little loss. Second, we introduce a concept of log-likelihood ratio (LLR)-based RPL ratio to determine the dominating overlap regions, and then propose a new nonuniform reference voltage sensing strategy. This strategy does not only reduce the memory sensing precision (i.e., the number of reference voltages), but also maintains the reliability of the soft information of NAND flash memory channel output for soft decoding. Third, we implement extensive simulations to verify the performance of the new nonuniform sensing strategy. The BER performances of LDPC codes for different sensing strategies are provided to show that the proposed LLR-based RPL-nonuniform sensing strategy can make a good compromise between memory sensing latency and error-correction performance.


Introduction
Today, in order to provide high-quality services to end users, data centers need fast and highly reliable storage. Multi-Level-Cell (MLC) NAND Flash memory has become a mainstream storage device due to its high performance and nonvolatile nature while reducing the over space and power. With the increased storage density of flash memory, memory blocks is increasingly susceptible to a variety of channel noises, including data retention, Cell-to-Cell interference (CCI), program/erase (P/E) cycles and read disturb (Cai, 2017;Cai, Luo, Ghose & Mutlu, 2015;Wang, Dong, Pan, Zhou & Stievano, 2011), which can shift the state threshold voltage. Consequently, the raw bit error rate of data stored in the memory increases. To improve the integrity and reliability of information stored in memory, error-correction codes (ECCs) are used, such as Bose-Chaudhuri-Hocquenghem (BCH), Reed-Solomon (RS) codes (Liu, Rho, & Sung, 2006;Micheloni, Ravasio, Marelli, Alice, Altieri, Bovino & Won, 2006) have been introduced to MLC NAND flash memory system. However, the traditional hard-decision ECCs are not enough to meet the reliability requirements of the high-density flash memory. Compared with hard-decision ECCs, soft decision based ECCs have a higher error-correcting performance, especially the low-density parity check (LDPC) codes (Gallager, 1962) which is a class of powerful iteratively decodable ECC. The Belief Propagation (BP) decoding algorithm of LDPC code is a typical iterative decoding algorithm that works iteratively. During iterations, the log-likelihood-ratio (LLR) soft information is iteratively updated to have excellent error performance in NAND flash memory. Therefore, the accuracy of the LLR value output by the NAND flash memory channel determines the decoding performance of the LDPC code.
For high-quality and accurate LLRs, NAND flash memory chips demand perform small range of soft-decision memory-cell sensing. However, fine-grained memory sensing can lead to an increase in the sensing time consumed by the chip and incur access latency penalty (Zhao, Dong, Sun, Zheng, & Zhang, 2012). Hence, it is necessary to make a trade-off between the memory sensing levels and decoding performance of flash memory chip. In addition to higher sensing precision, accurate channel initial LLRs also need to estimate the distribution of storage states. However, the threshold voltage distribution of storage states are severely shifted as the NAND flash chip scaling down and retention time increase (Prall, 2007). Literature (Lee, & Sung, 2013;Peng, Wang, Fu & Huo, 2017) study the distribution of varies noise and demonstrated that the distribution of each storage states can be approximately expressed as a Gaussian mixture function. Nonuniform sensing strategy (Dong, Xie & Zhang, 2011) is proposed to reduce memory sensing precision, yet gives a high precision within three dominating overlap region. However, only the cell-to-cell interference is regarded as the main noise in that work.
Our work attempts to overcome the shortcomings mentioned above. First, based on the channel model of NAND flash memory system, we use Monte Carlo to simulate flash memory with LDPC codes as ECC, which suffer from various noises, including cell-to-cell interference and retention time. We find the PDF of each state approximately obeys Gaussian distribution. Further, we derive mathematical formulations to estimate the parameters of state distributions. Second, combining the calculation of LLRs, we propose a new nonuniform sensing strategy based on the Relative-Precision-Loss (RPL) which can determine the boundary of dominating overlap regions. Final, we estimated the PDF of threshold voltage over a wide range of coupling strength factors s and different retention times T and calculated the LLRs of channel. Simulation results show that the proposed new nonuniform sensing strategy exhibits better error-correcting performance with respect to other existing counterparts while considering more noise interference.

NAND Flash Memory Channel
In the multi-level cell (MLC) NAND Flash memory, each cell is supposed to fall into one of the four non-overlapping threshold voltage windows and store 2 bits. Each threshold voltage window specifies one storage state, and the first state is the erased state storing 11, the other three states are the programmed states storing 10, 00 and 01, respectively. The smallest unit of erasure is a block, and all cells in a block should be erased before starting programming. Due to the inevitable process variability, the threshold voltage of the erased-state cell shifts, which is usually considered to be Gaussian distributed (Takeuchi, Tanaka & Nakamura, 1996;Wang, Dong, Pan, Zhou & Stievano, 2011). The PDF of the erased state threshold voltage is where e u and e  are the mean and the standard deviation, respectively. The incremental step pulse programming (ISPP) procedure is one common technique used to program memory cell (Suh, Lim, Kim, Choi, Koh & Lim, 1995). By the ISPP technique, the threshold-voltage distribution of the k-programmed state is uniform (Dong, Pan, & Zhang, 2014;Xu, Gong, Chen, Michael & Li, 2015), whose PDF is given by () where p V is the verify voltage of the -th k programmed state and pp V  is the incremental programming voltage step size.
In the MLC NAND Flash channel, there are many noise factors such as CCI, read disturb errors, random telegraph errors, retention time and P/E cycling errors, and various analytical methods are designed to work out with different noises. Among these factors, CCI is one sever noise, because the MLC technology reduces the width of threshold voltage for each storage state and narrows the gaps between adjacent states, which degrades the reliability of the memory. Retention noise is a predominant noise, especially when the flash device is powered-off for a long time or has been used with many P/E cycling operations. Hence, in our work, we mainly consider the flash memory with CCI and retention noise.

Cell-to-Cell Interference
For a memory chip, the Cell-to-Cell interference occurs due to parasitic capacitive coupling between adjacent memory cells. As the threshold voltage of a flash cell (interfering cell) increases, the threshold voltage of its adjacent (victim) cells also shift (Lee, Hur, & Choi, 2002). The unintended threshold voltage shifts may cause the victim cell moving into a different storage state, which brings data distortions. The charges change of the victim cell caused by CCI can be accurately modeled as a linear combination of the threshold voltage shift of the adjacent cells which are programmed after the victim cell . It can be expressed as  is the coupling-capacitive ratio between the -th n interfering cell and the victim cell, and is the threshold voltage change of the -th n interfering cell during programming. In addition, the computation of F  depends on the architecture of NAND Flash memory (Park, Kang, Kim, Hwang, Choi, Lee, Kim & Kim, 2008). In our work, we focused on NAND flash memories with all-bit-line structure where a victim cell is mainly disturbed by three neighboring cells on the next word-line, as shown in figure 1. Here, y  and xy  represent the vertical and diagonal coupling-capacitive ratios, respectively, which are assumed to be Gaussian According to the literature (Shibata, Maejima, 2008), the relation between of means of y  and xy  is set to be approximately 0.08:0.006, which shows that the vertical coupling ratio plays a major role in CCI. Therefore, we ignore the diagonal coupling ratio to simplify the following mathematics. To study a wide range of CCI, the parameter of cell-to-cell coupling strength factor s is introduced and the means of the verticality-coupling ratio and the diagonal-coupling ratio can be expressed as 0.08s and 0.006s, respectively. Supposing that the interfering cells be written to each state with the same probability (i.e., each state has the same probability of 1 K and 4 K  for MLC NAND flash memory), the PDF of CCI can be modeled as (Dong, Xie, Zhang, 2011) is the error-function and () x  represents the Dirac delta function. When the interfering cell remains in the erased state, it will not induce CCI to the victim cell. Hence, the corresponding interference is represented by Dirac delta function. Based on the above analysis, the PDF of the threshold-voltage for the victim cell that was programmed to the -th k programmed state and has been interfered by CCI can be expressed by where the sign  is the convolution operation. Supposing the victim cell is in the 0-th state (erased state), then the PDF () () k v px in (6) will be computed by using ()

Date Retention Noise
Retention noise (RN) is caused by charge leakage over time after a flash memory is programmed and repeated P/E operations. According to reference (Lee, Choi, Park & Kim, 2003;Cai, Yalcin, Mutlu, Haratsch, Cristal, Unsal & Mai, 2012;Cai, Yalcin, Mutlu, Haratsch, Crista, Unsal & Mai, 2013;Dong, Xie & Zhang, 2013), the retention noise can be approximated with a Gaussian distribution, whose PDF is given as where the mean rk u and the standard variance rk  are data-dependent and defined as (Dong, Xie & Zhang, 2013), as given by

The Mathematical Formula of LLR
Since the charges in a storage cell can be detected by finite number of sensing voltage, when probability density function of each storage state is available, it is easy to compute the initial LLR information for the flash memory channel. For MLC NAND flash memory, storing two bits in a cell, a physical page referring to all cells in one word-line consists of a least significant bit (LSB) page and a most significant bit (MSB) page. The left bit of the storing two bits is the MSB and the right one is the LSB. Recall that the four storage states 11, 10, 00 and 01 are denoted as the state 0,1, 2, and 3 k  , respectively. If a sensed threshold-voltage th V of memory cells falls into the reference voltage interval ( , ] lr RR , then the LLR information of the LSB and MSB are respectively calculated as (0) (1) (1) If a series of reference voltages is provided, then the above LLR information can be precalculated. If a soft decoding is performed, the calculated LLRs of channel are inputted to the LDPC decoder as initial soft-decision information. The decoding performance is affected by the choice of reference voltages. Therefore, it is critical to design a method to find (sub-) optimal reference voltages for soft decoding.

Gaussian Approximation of Threshold-Voltage Distribution
To compute the LLR informations in (11) and (12) To verify the validity of the above Gaussian approximation, we fit the distribution of storage states obtained by Monte-Carlo simulation with the derived Gaussian distribution. We find that the coincidence is high for a wide range of coupling strength factors. Figure 3 shows the similarity of the PDFs of the two kind distributions for two different coupling strength factor, i.e., 1.0 and 1.5 s  .

RPL-Nonuniform Memory Sensing Strategy
As mentioned in subsection 2.3, it is a key topic to find (sub-) optimal sensing voltages for soft decoding, because the error-correcting performance of soft decoding for LDPC codes is affected by the value of the LLR information as defined in formulas (11) and (12) that depends on the choice of sensing voltages ( , ] lr RR . In the literature of Dong et al. (2013), a nonuniform sensing strategy was designed to sense the dominating overlap area with a higher precision while the rest region with a lower precision. The dominating overlap region was determined by the borders that were selected by adjusting a probability ratio R of the adjacent two storage states based on entropy. The basic idea of the nonuniform sensing strategy is shown in Figure 4. The key of nonuniform sensing scheme is how to determine the boundary of the dominant overlapping regions of adjacent states. If each size of the dominant overlapping region is large, more sensing levels are introduced for better decoding performance, but heavier implementation and latency overhead is required. If the size of the dominant overlapping region is reduced, the number of sensing levels is reduced, but the performance of soft decoding may degrades. From computations of the LLR information defined by formulas (11) and (12), we find that each LLR is mainly dependent on two largest probability items in the overlapping region. In this work, by this observation, we introduce a concept of LLR-based relative-precision-loss (RPL) ratio . Then the boundary From the definition given by (17) and (18) And the corresponding boundaries of the dominant overlapping regions of every two adjacent storage states can be obtained at the same time. In each dominant overlapping region, a more fine-grained sensing with more voltage levels is adopted; but in the remainder region, a less precision sensing with less voltage levels is utilized. In this work, we apply the equal division to separate the sensing range between the hard-decision reference voltage and the neighbor boundary of the adjacent storage states. And each remainder region has no further division.

Simulation Results
In this subsection, we employ a rate-0.85(750, 5000) LDPC code in MLC NAND flash memory to evaluate the error correcting performance of soft decoding when the new nonuniform sensing strategy based on the LLR-based RPL ratios proposed in previous subsection is applied. For comparison, we also evaluate the soft decoding performances for the uniform sensing strategy presented by Alrod et. al in (2013) and the nonuniform sensing strategy based on entropy presented by Dong et.al in (2013) where the probability ratio R is set as 512 to determine the boundaries. In simulations, the parameters value of MLC NAND flash memory system are set as The CCI coupling strengthen factor s varies from 1.5 to 2.0 with the step size as 0.1. In simulations, we plot the BER performances of the proposed RPL-nonuniform sensing strategy, Dong's nonuniform sensing strategy and the traditional uniform sensing strategy under different sensing precisions. Figure 6 shows the BER versus the CCI. It can be observed that the proposed RPL-nonuniform sensing strategy http://cis.ccsenet.org Computer and Information Science Vol. 14, No. 2;2021 83 outperforms the traditional uniform sensing strategy, and that the BER performance of the proposed RPL-nonuniform sensing strategy enhances as the number of sensing levels increases. It can be seen that the proposed RPL-nonuniform sensing strategy outperforms Dong's nonuniform sensing strategy. For a given number (e.g., 15 and 31) of sensing levels, the performance advantage usually increases as the CCI coupling strength factor s becomes larger. This performance advantage may decrease as the number of sensing levels increases because of the more precise sensing for more levels. It can be seen also that, the performance of the proposed 15-level RPL-nonuniform sensing is close to that of 31-level uniform sensing, which shows that our proposed strategy reduces the sensing precision latency by about 45%.  Figure 7 shows the BER versus the retention time. It can be observed that, compared with the Dong's nonuniform sensing strategy and the traditional uniform sensing method, the proposed RPL-nonuniform sensing scheme can compensate the impact of retention time on the stability of flash memory cells to a greater extent.

Conclusion
In this paper, through Monte Carlo simulation, we discover that the threshold voltage disturbed by various noises (including CCI and RN) approximately to be Gaussian distributed, and then derive an easily-computable mathematical formulation to characterize the distribution of storage states. We further analyze the calculation of LLRs to introduce the parameter of relative-precision-loss ratio, and then propose a new nonuniform memory sensing strategy. With this sensing strategy, a series of reference voltages is obtained, and the soft-decoding LLRs for LDPC codes are evaluated. The proposed RPL-nonuniform sensing scheme still maintains the good anti-noises performance in MLC NAND flash memory while reducing the memory sensing level, which is also verified by a comprehensive simulation and comparison.