The Design of Efficient Viterbi Decoder and Realization by FPGA

Yan Yan Liu, Xiao hui Yang, Dian ren Chen

Abstract


Convolution code is a kind of widely used error-correcting codes in the error control field, in order to solve the Viterbi decoding of higher complex degree and lower speed etc. problem, a kind of efficient and reliable Viterbi decode method has been put forward specially. Firstly, the principle of Viterbi decode has been introduced by detail; Secondly, in order to improve the parallel decoding speed, Viterbi decoding algorithm is improved; And then, according to the improved algorithm to achieve high speed and parallel Viterbi decoding method, which is realized easily by FPGA; Finally, the function simulation and test for (2, 1, 7) convolution code has been carried out. The experimental results show that: when the system clock is 64 MHz, eventually the decoding rate of not less than 16 Mbps, improved Viterbi decoding algorithm has lower complexity, improved Viterbi decoding efficiency.


Full Text: PDF DOI: 10.5539/mas.v6n11p44

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Modern Applied Science   ISSN 1913-1844 (Print)   ISSN 1913-1852 (Online)

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